Director of Applications Engineering

Role Overview

Director of Applications Engineering for high-power GaN-based power management solutions (Smart Power Stages and controllers) powering CPUs and GPUs in AI data center architectures. This is a hands-on technical leadership role spanning bench characterization, system validation, and customer technical enablement, bridging silicon design, multi-die packaging, product/test engineering, and tier-1 computing clients.

Responsibilities

• Bench characterization & diagnostics: Lead lab testing, debugging, and performance optimization of Smart Power Stages, driver ICs, and multiphase controllers under real-world AI workload dynamics.
• Silicon & GaN evaluation: Benchmark and optimize high-frequency, high-power-density Si and GaN power stages for power density, transient response, efficiency, and thermal behavior.
• Cross-functional collaboration: Work with IC design, package engineering, systems engineering, and product/test teams to translate system requirements into silicon/module definitions and resolve silicon/packaging anomalies.
• Packaging & thermal integration: Provide application-level feedback on advanced power packaging (e.g., QFN, LGA, FO-PLP, and chip-/substrate-embedded architectures).
• Customer technical advocacy: Create reference designs, evaluation boards (EVBs), application notes, and provide direct technical engineering support to hyperscale and server OEM/ODM teams.

Required Qualifications

• Education: B.S. in Electrical Engineering (M.S./Ph.D. preferred) focused on Power Electronics.
• Experience: 10+ years hands-on experience in high-power management IC development and application engineering.
• Domain expertise: Track record in high-density power solutions for AI servers, GPUs, CPUs, and enterprise computing.
• Deep mastery of Si-based MOSFET/IC topologies and GaN power devices.
• Familiarity with multiphase buck converters, switched-capacitor architectures, and point-of-load (PoL) topologies.
• Lab skills: Bench testing, high-bandwidth signal integrity measurements, loss breakdown analysis, thermal imaging, and high-frequency noise troubleshooting.
• Packaging knowledge: Understanding of power module assembly, parasitic inductance minimization, thermal dissipation paths, and layout constraints for LGA, QFN, FO-PLP, and embedded-chip packages.
• Industry experience: Experience with leading power semiconductor companies (e.g., Infineon, Renesas, MPS, AOS, Analog Devices, or similar).

Preferred Qualifications

• Experience with power delivery architectures for low-voltage, ultra-high-current processor rails (e.g., sub-1V, 500A+ transient profiles).